1. Field of the Invention
The present invention generally relates to a semiconductor device, and particularly relates to a semiconductor device which is improved for increasing performance and reliability. The invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In recent years, a flash memory which is a kind of nonvolatile semiconductor memory device has been expected as a useful memory device for the next generation because it can be manufactured at a lower cost than a Dynamic Random Access Memory (DRAM), and therefore.
FIG. 59 is a cross section of a memory cell portion of a flash memory in the prior art.
The structure in FIG. 59 is provided at a surface of a semiconductor substrate 1 with a source region 2 connected to a source line and a drain region 3 connected to a corresponding bit line. A floating gate electrode 5 is arranged on semiconductor substrate 1 with a tunnel oxide film 4 therebetween. A control gate electrode 7 which is connected to a corresponding word line is arranged on floating gate electrode 5, and a control gate and floating gate interlayer insulating film 6, which is generally formed of an oxide film, a nitride film and an oxide film (ONO film), is interposed between control gate electrode 7 and floating gate electrode 5.
An FN (Fowler-Nordheim) current phenomenon, a Channel Hot Electron (CHE) phenomenon or the like is caused in tunnel oxide film 4, which is located immediately under floating gate electrode 5, for injecting electrons into floating gate electrode 5 or removing electrons therefrom so that erasing or writing is performed. Depending on the state of electrons in floating gate electrode 5, the binary state of the threshold is determined, and the xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is read out depending on this state.
In the nonvolatile semiconductor memories of the floating gate type such as a flash memory described above and an EEPROM, NOR-type array structures are used most generally. In the NOR-type array, contacts are formed in a drain diffusion layer of memory cells in each row, and bit lines formed of metal interconnections or polycide interconnections are arranged in the row direction. Thus, the NOR-type array structure has the gate interconnections of the memory cells in the respective columns and the bit line are, which are arranged in a matrix form.
FIG. 60 is a circuit diagram showing the NOR-type array. FIG. 61 shows a layout of the NOR-type array.
FIG. 62 is a cross section taken along line Axe2x80x94A in FIG. 61. FIGS. 62 and 63 are cross sections taken along lines Bxe2x80x94B and Cxe2x80x94C in FIG. 61, respectively. In these figures, xe2x80x9c8xe2x80x9d indicates a bit line contact, xe2x80x9c9xe2x80x9d indicates an active region, xe2x80x9c10xe2x80x9d indicates an isolating oxide film, and xe2x80x9c11xe2x80x9d indicates an oxide film.
Referring to these figures, all source regions 2 of memory cells in each block, which is formed of memory cells of, e.g., 512 Kbits, are connected. For connecting all source regions 2 in this manner, a self-align source structure may be used very effectively for miniaturizing the memory cells.
For connection of source region 2 of each memory cell, the self-align source structure does not employ such a manner that a contact is extended to a diffusion layer of each memory cell, and the contacts thus formed are connected by metal interconnections. In the self-align source structure, as shown in FIG. 65, control gate electrodes 7 of the memory cells are first formed, and resists 12 having openings which expose only source regions 2 are formed. Ends of resists are located on control gate electrodes 7. Referring to FIGS. 65 and 64, etching is effected on a structure masked with resists 12 and control gate electrodes 7 so that an isolating oxide film which is present in source regions 2 is removed. Further, ion implantation of arsenic or the like is effected on source regions 2. Thereby, source regions 2 are connected together in the column direction by the diffusion layer. These are formed in a self-aligned fashion. In FIG. 64, dotted lines represent portions of the isolating oxide film which are removed by the etching.
All the source regions of the memory cells may be formed of the active regions, and may be connected by metal interconnections. This structure requires an alignment margin so that a gate distance in the source region must be large. In the self-align source technique, however, all the source regions of the memory cells are formed of the active regions, and are connected by the diffusion layers so that the distance between the gates located on the opposite sides of the source region in the memory cell can be determined in accordance with the minimum design rule. Thus, the miniaturization of the memory cells can be achieved.
In accordance with remarkable reduction in design rule in recent years, however, it is required in the flash memory employing the self-align source structure to reduce further the distance between the gates on the opposite sides of the source region of the memory cell, which can be formed in accordance with the minimum design rules.
For performing the write and erase operations in the flash memory, an FN tunnel current or a CHE tunnel current must be produced on the control gate electrode, source/drain and substrate. For this, a high voltage of 10 V or more is required. For handling such a high voltage, a peripheral transistor must have a higher breakdown voltage than a peripheral transistor used in a DRAM or an SRAM.
A high breakdown voltage of the transistor can be effectively achieved by optimizing a source/drain structure and employing a thick sidewall spacer.
Referring to FIG. 66, if a thick sidewall is used in a flash memory device having a miniaturized structure for achieving a peripheral circuit having a high breakdown voltage, the sidewall spacer fills a narrow space located on source region 2 and formed between neighboring gates in the memory cell. In this case, a stress is caused and applied to the substrate due to expansion and contraction of the sidewall insulating film filling the narrow space on source region 2 during later processing of oxidation and high-temperature annealing. As a result, crystal defects 13 occur in substrate 1. Consequently, leakage occurs between the source and drain of the memory cell, resulting in remarkable reduction in device performance. If crystal defects 13 extend to a position under tunnel oxide film 4, reliability such as endurance and retention remarkably lower.
FIG. 67 shows a flow from formation of the layered gate to formation of the sidewall spacer in a first prior art.
Referring to FIG. 68, first and second layered gates 20a and 20b are formed. Referring to FIG. 69, a resist pattern 28 having an opening exposing only the source portion of the cell is formed by photolithography. Using resist pattern 28 as a mask, etching is effected to remove the isolating oxide film, and ion implantation is performed for providing the diffusion layer interconnection in the etched portion. Thereby, the self-align sources is completed. Referring to FIG. 70, resist pattern 28 is removed. Referring to FIG. 71, an insulating film 14 for forming a sidewall spacer, which will be referred to as a xe2x80x9csidewall insulating filmxe2x80x9d hereinafter, is deposited. Referring to FIG. 72, sidewalls of floating gates 5 and control gates 7 are oxidized for the purpose of rounding the ends on both the source and drain sides of floating gates 5. Referring to FIG. 73, etch-back is effected on sidewall insulating film 14.
In the prior art shown in FIG. 72, sidewall insulating film 14, which is located on source region 2 and between the gates, expands and contracts to apply a stress to the substrate portion located under source region 2 when thermal processing for a high-temperature oxidization of the sidewall is performed in an oxygen atmosphere at 800-900xc2x0 C. This stress causes crystal defects 13 shown in FIG. 66.
FIG. 74 is a flow showing a second prior art.
Referring to FIG. 75, processing is performed to form first and second layered gates 20a and 20b, and the self-align source step (photolithography +etching+ion implantation+resist removal) is completed. Thereafter, oxidization is effected on sidewalls of floating gates 5 and control gates 7. Referring to FIG. 76, the sidewall insulating film is deposited, and is etched back.
According to this prior art, the crystal defect shown in FIG. 66 does not occur. As shown in FIG. 75, however, polycrystalline silicon of layered gates 20a and 20b are exposed when the sidewalls thereof are oxidized. Therefore, the polycrystalline silicon of layered gates 20a and 20b are oxidized to a larger extent than the first prior art so that the substantial gate length increases. Thereby, punch-through occurs in the memory cell. Further, the sidewalls of the floating gate and control gate are oxidized to extents which vary depending on differences in concentration of the polycrystalline silicon so that the coupling ratio of the memory cells lowers. This results in deterioration of write and erase speeds.
The foregoing problem relating to the crystal defect occurs not only in the manufacturing of flash memories but also in the manufacturing of ordinary MOS transistors. Referring to FIG. 77, a space between gates 15 and 16 is fully filled with a sidewall insulating film (CVD-SiO2 (TEOS)) 17. In this structure, sidewall insulating film 17 expands and contracts during later thermal processing so that a stress is applied to substrate 1 and crystal defects 13 occur.
The invention has been made for overcoming the above problems, and it is an object of the invention to provide an improved semiconductor device, in which crystal defects do not occur, and reliability is increased.
Another object of the invention is to provide an improved flash memory having increased reliability.
Still another object of the invention is to provide an improved MOS transistor having increased reliability.
Yet another object of the invention is to provide a method of manufacturing such a semiconductor device.
A semiconductor device according to a first aspect of the invention includes first and second gates formed on a substrate and spaced from each other. A sidewall spacer having a configuration determined to prevent application of a stress to the substrate is arranged on sidewalls of the first and second gates.
The semiconductor device according to a second aspect of the invention includes first and second layered gates arranged on a semiconductor substrate, spaced from each other and each having a floating gate and a control gate layered together. A source region located between the first and second layered gates is arranged at a surface of the semiconductor substrate. A first drain region is formed at the surface of the semiconductor substrate, and is located in a position remote from the source region with the first layered gate therebetween. A second drain region is arranged at the surface of the semiconductor substrate, and is located in a position remote from the source region with the second layered gate therebetween. A sidewall spacer is arranged on sidewalls of the first and second layered gates neighboring to the drain region. No sidewall spacer is arranged on sidewalls of the first and second layered gates neighboring to the source region.
The semiconductor device according to a third aspect of the invention includes first and second layered gates arranged on a semiconductor substrate, spaced from each other and each having a floating gate and a control gate layered together. A source region located between the first and second layered gates is arranged at a surface of the semiconductor substrate. A first drain region is formed at the surface of the semiconductor substrate, and is located in a position remote from the source region with the first layered gate therebetween. A second drain region is arranged at the surface of the semiconductor substrate, and is located in a position remote from the source region with the second layered gate therebetween. A first sidewall spacer is arranged on the opposite sidewalls of the first layered gate. A second sidewall spacer is arranged on the opposite sidewalls of the second layered gate. A thermal oxide film is present immediately under the first and second sidewall spacers and at the surface of the source region and the surfaces of the first and second drain regions.
The semiconductor device according to a fourth aspect of the invention includes first, second and third gate electrodes successively aligned and formed parallel to each other on the semiconductor substrate. A distance between the first and second gate electrodes is smaller than a distance between the second and third gate electrodes. A sidewall spacer is arranged on a sidewall of the second gate electrode neighboring to the third gate electrode. The distance between the first and second gate electrodes is smaller than double the thickness of the sidewall spacer.
In the semiconductor device according to a fifth aspect of the invention, the sidewall spacer is formed of a nitride film, and contact holes connected to the first and second drain regions, respectively, are formed in a self-aligned fashion.
In the semiconductor device according to a sixth aspect of the invention, the sidewall spacer made of the nitride film is formed on a sidewall of each of the first and second gate electrodes with a buffer layer therebetween. The sidewall spacer made of the nitride film is arranged on the semiconductor substrate with a buffer layer therebetween.
The semiconductor device according to a seventh aspect of the invention includes a peripheral circuit portion having a gate electrode, and a cell portion. The cell portion has first and second layered gates spaced from each other, and each formed of a floating gate and a control gate layered together. A sidewall spacer is arranged on a sidewall of the gate electrode. A distance between the first and second layered gates is smaller than double the width of the sidewall spacer. No sidewall spacer is formed on sidewalls of the first and second layered gates.
The semiconductor device according to an eighth aspect of the invention includes a peripheral circuit portion having a gate electrode, and a cell portion. The cell portion has first and second layered gates spaced from each other, and each formed of a floating gate and a control gate layered together. A first sidewall spacer is arranged on a sidewall of the gate electrode. A distance between the first and second layered gates is smaller than double the width of the first sidewall spacer. A second sidewall spacer having a thickness smaller than half the distance between the first and second layered gates is formed on sidewalls of the first and second layered gates.
In a method of manufacturing a semiconductor device according to a ninth aspect of the invention, first and second gates spaced from each other are formed on a substrate. A sidewall spacer having a configuration determined to prevent application of a stress to the substrate is formed on sidewalls of the first and second gates.
In the method of manufacturing a semiconductor device according to a tenth aspect of the invention, first and second layered gates spaced from each other with a common source region therebetween and each having a floating gate and a control gate layered together are formed on the semiconductor substrate. A sidewall spacer formation insulating film covering the first and second layered gates is formed on the semiconductor substrate. Etch-back is effected on the sidewall formation insulating film to form a sidewall spacer on sidewalls of the first and second layered gates neighboring to the drain region. The sidewall spacer formation insulating film and an isolating oxide film located between the first and second layered gates and neighboring to the source are simultaneously removed by etching in a self-aligned manner. Sidewalls of the floating gate and the control gate are oxidized.
In the method of manufacturing a semiconductor device according to an eleventh aspect of the invention, first and second layered gates spaced from each other with a common source region therebetween and each formed of a floating gate and a control gate layered together are formed on a semiconductor substrate. Sidewalls of the floating gate and the control gate are oxidized. A sidewall spacer formation insulating film covering the first and second layered gates is formed on the semiconductor substrate. Etch-back is effected on the sidewall spacer formation insulating film to form a sidewall spacer on sidewalls, neighboring to the drain, of the first and second layered gates. The sidewall spacer formation insulating film and an isolating oxide film located between the first and second layered gates and neighboring to the source are simultaneously removed by etching in a self-aligned manner.
In the method of manufacturing a semiconductor device according to a twelfth aspect of the invention, first and second layered gates spaced from each other with a common source region therebetween and each formed of a floating gate and a control gate layered together are formed on a semiconductor substrate. A sidewall spacer formation insulating film covering the first and second layered gates is formed on the semiconductor substrate. Etch-back is effected on the sidewall spacer formation insulating film to form a sidewall spacer on sidewalls, neighboring to the source region and the drain region, of the first and second layered gates. Sidewalls of the floating gate and the control gate are oxidized, and at the same time a thermal oxide film is formed on surfaces of the source region and the drain region.
In the method of manufacturing a semiconductor device according to a thirteenth aspect of the invention, first, second and third gate electrodes successively aligned are formed parallel to each other on the semiconductor substrate. A sidewall spacer formation insulating film covering the first, second and third gate electrodes is formed on the semiconductor substrate. A resist pattern exposing a portion located between the first and second gate electrodes and covering the other portion is formed on the semiconductor substrate. Using the resist pattern as a mask, etch-back is effected on the sidewall spacer formation insulating film to form a first sidewall spacer on the sidewalls opposed to each other of the first and second gate electrodes. The resist pattern is removed. Etch-back is effected on the remaining sidewall spacer formation insulating film to form a second sidewall spacer on the sidewalls remote from each other of the first and second gate electrodes. A distance between the first and second gate electrodes is smaller than double the thickness of the second sidewall spacer.
In the method of manufacturing a semiconductor device according to a fourteenth aspect of the invention, first and second layered gates spaced from each other with a common source region therebetween and each formed of a floating gate and a control gate layered together are formed on a semiconductor substrate. A nitride film covering the first and second layered gates is formed on the semiconductor substrate. Etch-back is effected on the nitride film to form a sidewall spacer made of the nitride film on sidewalls remote from each other of the first and second gate electrodes. A resist pattern exposing a portion located between the first and second layered gates and covering the other portion is formed on the semiconductor substrate. Using the resist pattern as a mask, the nitride film and an isolating oxide film located between the first and second layered gates and neighboring to the source are removed by etching. Sidewalls of the floating gate and the control gate are oxidized.
In the method of manufacturing a semiconductor device according to a fifteenth aspect of the invention, first and second layered gates spaced from each other with a common source region therebetween and each formed of a floating gate and a control gate layered together are formed on a semiconductor substrate. Sidewalls of the floating gate and the control gate are oxidized. A nitride film covering the first and second layered gates is formed on the semiconductor substrate. Etch-back is effected on the nitride film to form sidewall spacers made of the nitride film on sidewalls remote from each other of the first and second gate electrodes. A resist pattern exposing a portion located between the first and second layered gates and covering the other portion is formed on the semiconductor substrate. Using the resist pattern as a mask, the nitride film and an isolating oxide film located between the first and second layered gates and neighboring to the source are removed by etching.
In the method of manufacturing a semiconductor device according to a sixteenth aspect of the invention, first and second layered gates spaced from each other with a common source region therebetween and each formed of a floating gate and a control gate layered together are formed on a semiconductor substrate. A plasma oxide film or a CVD film covering the first and second layered gates is formed. A nitride film covering the first and second layered gates is formed on the semiconductor substrate. Etch-back is effected on the nitride film to form sidewall spacers made of the nitride film on sidewalls remote from each other of the first and second gate electrodes. A resist pattern exposing a portion located between the first and second layered gates and covering the other portion is formed on the semiconductor substrate. Using the resist pattern as a mask, the nitride film and an isolating oxide film located between the first and second layered gates and neighboring to the source are removed by etching. Sidewalls of the floating gate and the control gate are oxidized.
In the method of manufacturing a semiconductor device according to a seventeenth aspect of the invention, first and second layered gates spaced from each other with a common source region therebetween and each formed of a floating gate and a control gate layered together are formed on a semiconductor substrate. Sidewalls of the floating gate and the control gate are oxidized. A plasma oxide film or a CVD film covering the first and second layered gates is formed. A nitride film covering the first and second layered gates is formed on the semiconductor substrate. Etch-back is effected on the nitride film to form sidewall spacers made of the nitride film on sidewalls remote from each other of the first and second gate electrodes. A resist pattern exposing a portion located between the first and second layered gates and covering the other portion is formed on the semiconductor substrate. Using the resist pattern as a mask, the nitride film and an isolating oxide film located between the first and second layered gates and neighboring to the source are removed by etching.
In the method of manufacturing a semiconductor device according to an eighteenth aspect of the invention, a gate is formed in a peripheral circuit portion on the semiconductor substrate. A sidewall spacer is formed on a sidewall of the gate. First and second layered gates spaced from each other with a common source region therebetween and each formed of a floating gate and a control gate layered together are formed in a cell portion on the semiconductor substrate.
In the method according to a nineteenth aspect of the invention, a second sidewall spacer having a thickness smaller than that of the sidewall spacer and equal to xc2xd or less of the distance between the first and second layered gates are formed on the opposite sidewalls of the first layered gate and the opposite sidewalls of the second layered gate.